1. Field of the Invention
The present invention relates a semiconductor IC.
The present invention particularly concerns a semiconductor IC including high speed bipolar transistors.
2. Description of the Prior Art
A semiconductor IC generally comprises transistors and npn transistors in a monolithic construction. The npn transistors generally have high switching speed, while the pnp transistors are not suitable for high speed switching since they have been previously implemented in a vertical structure, a more complex construction than the npn transistors. Accordingly, in a semiconductor IC including both the pnp transistors and npn transistors, full high speed performance of the npn transistors cannot be achieved due to imbalance between the two types of transistors and the circuit design also has many limitations.
FIG. 1 shows a sectional configuration of a prior art semiconductor IC including pnp transistors and npn transistors in a monolithic configuration.
In FIG. 1 numeral 1 designates a p-type substrate, numeral 2 designates a high concentration n-type buried region, numeral 3 designates an n-type epitaxial layer, numeral 4 designates a diffused isolation region, numeral 5 designates a diffused isolation region formed from the surface of the epitaxial layer 3 and which is connected with the isolation diffused region 4 to serve as the isolation between the active regions.
P-type diffused regions 6e, 6c and 7b are formed simultaneously. The p-type region 7b is a base region of an npn transistor part, and p-type regions 6e and 6c are the emitter region and collector region of the lateral pnp transistor part. High impurity concentration n.sup.+ -type region 8b, 9e and 9c are base contact regions for the lateral pnp transistor, emitter region of the vertical npn transistor and collector contact region of the vertical npn transistor, respectively. In the vertical npn transistor and lateral pnp transistor formed monolithically as shown in FIG. 1, achievable minimum base width (distance between the p-type region 6e and p-type region 6c) is determined by the accuracy of the plan view pattern, namely accuracy of the mask pattern used for a lithographic method. In general, the mask accuracy is not so high, and accordingly the achievable minimum base width has been about 3 .mu.m. Therefore, it has been impossible to manufacture highly integrated pnp transistors on the bipolar IC. On the other hand in the npn transistor part, the base region 7b has graded impurity concentration with respect to depth, accordingly a graded electric field is formed in the base region 7b, thereby carriers are accelerated to achieve high speed performance. However, in the lateral pnp transistor part, no graded concentration is formed in the base region 3 which is the epitaxial layer as such, therefore the above-mentioned carrier acceleration by means of graded concentration is impossible. Furthermore, the collector region 6c of the pnp transistor has rather higher concentration than that of the base region 3, accordingly when the base width is shortened a collector-base breakdown voltage is very much lowered.
As has been elucidated, the prior art IC having a lateral pnp transistor and vertical npn transistor on a monolithic chip has such shortcomings that achievable minimum base width is not sufficiently short, therefore there is no graded impurity concentration profile. Hence no graded electric field is produced and concentrations of the emitter region and collector region of the lateral pnp transistor have to be equal to each other. Therefore, as a result of these reasons, the lateral pnp transistor part generally has very poor characteristics in comparison with the vertical npn transistor part. Accordingly the semiconductor IC as shown in FIG. 1, as a whole, cannot achieve satisfactory characteristics.
In order to improve the above-mentioned drawback of the semiconductor IC of FIG. 1, another improvement has been proposed as shown in FIG. 2. The semiconductor IC shown in FIG. 2 is characterized by a vertical pnp transistor part. In FIG. 2, numeral 11 designates a p-type substrate, numeral 12 designates a high concentration n-type buried region, numeral 13 designates an n-type epitaxial layer, numeral 14 designates a diffused p.sup.+ -type isolation region, and numeral 15 designates a p.sup.+ -type diffused isolation region. Two isolation regions 14 and 15 together form an isolation region to surround the active region. Numeral 16 designates a p.sup.+ -type region formed on an n.sup.+ -type buried region 12, and the p.sup.+ -type region 16 forms a collector region of this vertical pnp transistor part. The n-type epitaxial layer 13 forms a base region. The numerals 17 and 18 are p.sup.+ -type regions formed simultaneously with forming of the p.sup.+ -type regions 14 and 15, respectively, and the p.sup.+ -type regions 17 and 18 form lead out regions for the collector region 16. Numerals 19, 19 designate walls. Numeral 20 designates a p.sup.+ -type diffused region which is formed simultaneously with the isolation regions 15 and serves as an emitter region of the vertical pnp transistor part.
In the npn transistor part, n.sup.+ -type region 21 is the emitter region, p-type diffused region 22 is the base region, and n.sup.+ -type diffused region 19' together with n.sup.+ region 23 form a collector contact.
In the configuration of FIG. 2, a vertical pnp transistor is formed with a p.sup.+ -type diffused region as emitter, n-type epitaxial layer 13 to be led out by n.sup.+ -region 19 as the base, and p.sup.+ -type buried region 16 as the collector. Apart from the lateral pnp transistor as shown in FIG. 1, this vertical pnp transistor has a base width which is determined by the vertical width of the n-type region 13 between the p.sup.+ -type diffused region 20 and the p.sup.+ -type buried region 16. And the base width is dependent on the depth of the p.sup.+ -type diffused region 16, thickness of the n-type epitaxial layer 13 and diffusion depth of the p.sup.+ -type diffused region 20, and not determined by the mask size or accuracy of the mask. Accordingly, the base width can be made very narrow. However, this configuration has several shortcomings. Firstly, the base width which is determined by the above-mentioned three sizes, depends on parameters of the three diffusions and therefore, accurate control is very difficult. Secondly, since the impurity concentration of the p.sup. + -type diffusion region 16 is determined as a difference between the impurities of n.sup.+ -type buried region 12 and the p.sup.+ -type impurity to be diffused in the region 16, the upward diffusion of the p.sup.+ -type region 16 is determined not only by the doping value of the p.sup.+ -type impurity. Therefore, it is difficult to control the upper surface of the p.sup.+ -type region 16. Therefore, the base width accuracy is difficult to achieve. Thirdly, this configuration can not provide graded impurity concentration in the base region, and also the impurity concentration of the collector region 16 is still high. Thus the configuration of the prior art of FIG. 2 has not been satisfactory.
FIG. 3 shows another prior art configuration wherein a vertical pnp transistor and a vertical npn transistor are formed in combination, wherein corresponding parts to the parts in the prior art example FIG. 2 are shown by the same reference numerals. In the prior art of FIG. 3, n.sup.+ -region 24 is connected to buried n.sup.+ -region 12, and n.sup.+ -region 24 is the emitter lead out region for IIL npn transistor. The IIL npn transistors are formed with n.sup.+ -type diffused regions 27-1 and 27-2 as collectors, p-type diffused region 26 as base regions and n-type epitaxial region 13 as emitter regions which are led out through the buried n.sup.+ -region 12 and diffused n.sup.+ -region 24. An IIL pnp transistor is formed by a p-type diffused region 25 as emitter (injector), n-type epitaxial region 13 as base region, and the p-type diffused region 26 as the collector. The p-type regions 25 and 26 are formed in a step corresponding to forming a base region 22 of the npn transistor in FIG. 2. The n.sup.+ -type collector regions 27-1 and 27-2 are formed in a step corresponding to forming of the emitter region 21 in the case of FIG. 2.
In the IIL as shown in FIG. 3, since the emitter contact region 24 contacts low impurity concentration epitaxial layer 13, a large number of holes as minority carriers are injected from the base region 26 to the emitter region 13. As a result, current amplification factor of the vertical npn transistors is not high, and the speed of the IIL becomes slow. If impurity concentration of the epitaxial layer 13 is raised, it will result in lowering its breakdown voltage of the vertical npn transistor.
As has been elucidated with reference to FIG. 2 which has a vertical pnp transistor and a vertical npn transistor and FIG. 3 which has IIL, fulfilling of high speed and high breakdown voltage at the same time in the prior art configuration has been difficult.
FIG. 4 shows still another prior art example of a bipolar transistor combined with CMOS transistor. In FIG. 4, parts corresponding to the preceding prior art art examples are designated with corresponding reference numerals. The p-well regions 14a+15a are formed simultaneously with forming of the diffused isolation region 14 and diffued region 15, respectively. Thereafter, source region 28 and drain region 28' of a p-channel MOS FET are formed simultaneously with forming of base region 22 of vertical npn transistor 22. And source region 29 and drain region 29' of an n-channel MOS FET are formed simultaneously with forming of the emitter region 21 of the vertical transistor. Gate oxide films 30-1 and gate electrodes 30-2 are formed.
In the above-mentioned prior art IC, diffusion depths of the source region 28 and drain region 28' the same as that of the base region 22 of the vertical npn transistor. Therefore, therefore the diffusion depth is too deep for the source region 28 or drain region 28'. Accordingly, effective channel distance l becomes too short, thereby source-drain breakdown voltage is liable to be lowered, or the threshold value (V.sub.T) lowered as a result of short-channel effect. Alternatively, in order to prevent the above-mentioned short-channel effect, resistivity of the epitaxial layer 13 may be lowered, but such lowering of the resistance of the epitaxial layer 13 will produce a problem that emitter-collector breakdown voltage of the vertical pnp transistor is lowered.